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    CMOS digital imeyatcd circuits: analysis:md d lgn I Sung-Mo (Sit' ·c) Kang. . VLSI Circuits, Physical Design for Multichip Modules, and Modeling of Electrical. Kang vlsi. 1. Physical and Materials Constants Boltzmann's constant Electron charge Thermal voltage Energy gap of silicon (Si) Intrinsic carrier. Sung Mo Kang, Leblebici - Ebook download as PDF File .pdf) or read book online. Principles of CMOS VLSI Design - A Systems Perspective (Neil Weste.

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    Kang Vlsi Pdf

    S.M. Kang and Y. Leblebici. Copyright © The McGraw-Hill Companies since its first introduction, but the term VLSI remained virtually universal to denote digital. Its an PDF file of VLSI book By KANG as Author thus do have a look. Useful book on VLSI (Very large scale integration) by Kang Full Ebook which covers all chapters.

    Free shipping for individuals worldwide Usually dispatched within 3 to 5 business days. The assessment and improvement of reliability on the circuit level should be based on both the failure mode analysis and the basic understanding of the physical failure mechanisms observed in integrated circuits. A thorough understanding of the physical mechanisms leading to hot-carrier related degradation of MOS transistors is a prerequisite for accurate circuit reliability evaluation. It is also being recognized that important reliability concerns other than the post-manufacture reliability qualification need to be addressed rigorously early in the design phase. The development and use of accurate reliability simulation tools are therefore crucial for early assessment and improvement of circuit reliability : Once the long-term reliability of the circuit is estimated through simulation, the results can be compared with predetermined reliability specifications or limits. If the predicted reliability does not satisfy the requirements, appropriate design modifications may be carried out to improve the resistance of the devices to degradation.

    Kahng or Jeff Woods, jewoods eng. June 5, Prof. June 2, Prof. May 29, Prof. May 17, Congratulations to Dr. May 16, Prof. Kahng will receive the Ho-Am Prize in Engineering, in recognition for the ennoblement of the human spirit in academics, the arts, and human welfare link [cached].

    March 22, Prof. March 21, Prof. March 19, Prof. January 21, Prof. December 14, Congratulations to Hyein Lee on filing her Ph. Kudos to Kwangsoo Han, Dr. Kahng gave an overview talk on the Design Enablement thrust of the center. Kudos to Mingyu Woo for all his hard work on this. November 15, Congratulations to Kwangsoo Han on passing his Ph. D defense!!! November 14, Congratulations to Hyein Lee on passing her Ph. Kudos to Hyein Lee, Dr. Jiajia Li and Minsoo Kim for all their hard work on this!

    The software is open source, licensed under GPLv3. Kudos to James Cherry for all his effort to make this happen, and for his willingness to provide this timer to the world! September 13, Prof. August 1, We are happy to announce that the RePlAce global placement tool repository on github is now public.

    Kudos to Lutong Wang, Dr. The alternate circuit diagram obtained by applying this principle of symmetry in shown in Fig. Note that the Boolean functions realized by the circuits shown inFig. These issues will be discussed in detail in Chapter 7. This initial sizing of transistors, which is obviously not an optimum solution, may be changed later depending on the performance characteristics of the adder circuit. Choos- ing minimum-size transistors in the initial design stage usually provides a simple, first- cut verification of the circuit functionality and helps the designer in developing a simple initial layout.

    V-n sum Figure1. Transistor-level schematic of the one-bit full-adder circuit. VDD Figure1. Alternate transistor-level schematic of the one-bit full-adder circuit note that the nMOS and pMOS networks are completely symmetric. Next, the initial layout of the full-adder circuit is generated. Here we use a regular, gate-matrix layout style in order to simplify the overall geometry and the signal routing.

    The initial layout using minimum-size transistors is shown in Fig. Note that in this initial adder cell layout, all nMOS and pMOS transistors are placed in two parallel rows, between the horizontal power supply and the ground lines metal. All polysilicon lines are laid out vertically. The area between the n-type and p-type diffusion regions is used for running local metal interconnections routing. Also note that the diffusion regions of neighboring transistors have been merged as much as possible, in order to save chip area.

    Theregular gate-matrix layout style used in this example also has the inherent advantage ofbeing easily adaptable to computer-aided design CAD.

    Initial layout of the full-adder circuit using minimum-size transistors. The designer must confirm, using an automatic design rulechecker DRC tool, that none of the physical layout design rules are violated in this adder layout. This is usually done concurrently during the graphical entry of the layout. The next step is to extract the parasitic capacitances and resistances from the initial layout, and then to use a detailed circuit simulation tool e.

    VLSI book By KANG pdf Free Download

    SPICE to estimate the dynamic performance of the adder circuit. Thus, we are now in the design verification stage of the design-flow diagram shown in Fig. The parasitic extraction tool reads in the physical layout file, analyzes the various mask layers to identify transistors, interconnects and contacts, calculates the parasitic capacitances and the parasitic resistances of these structures, and finally prepares a SPICE input file that accurately describes the circuit see Chapter 4.

    The extracted circuit file is now simulated using SPICE in order to determine its dynamic performance. The three input waveforms A, B and C are chosen so that all of the eight possible input combinations are applied consecutively to the full-adder circuit. Assuming that the outputs of this adder circuit may drive a similar circuit, both output nodes are loaded with capacitors which represent the typical input capacitance of a full adder.

    Unfortunately, the 13 Introduction CarryOUT 5.

    SUM 1. Simulated input and output waveforms of the full-adder circuit. In particular, the worst-case delay is found to be about 2. Design modifications will be necessary to correct this problem. Thus, we go back to the layout design stage. One approach to increase switching speed, and thus, toreduce delay times, would be to increase the WIL ratios of all transistors in the circuit. However, increasing the transistor WIL ratios also increases the gate, source, and drain areas and, consequently, increases the parasitic capacitances loading the logic gates.

    I -S Also, one should be careful to consider all possible input tra Optimiing te propagation delay for one particular input transition only may resuina unintended ices fpoaain eay uigohrtastos F iger1. Thus, th 18 19 20 21 22 23 24 25 Time [nsl Figure 1.

    Simulated output waveforms of the full adder circuit with minimum transistor dimensions, showing the signal propagation delay during one of the worst-case transitions.

    While we resize the nMOS and pMOS transistors in the full-adder circuit to meet the timing requirements, we can also reorganize the whole layout in order to achieve a more compact placement, to increase silicon area utilization, and to reduce the interconnection parasitics within the cell.

    The resulting cell layout is shown in Fig. For the optimized full-adder circuit, we find that all propagation and transition rise and fall delay times are now within the specified limits, i. Note that the propagation delay is about 1. The dynamic power dissipation of this circuit is estimated to be lW. Thus, the circuit now satisfies the design specifications given in the beginning.

    Modified layout of the full-adder circuit, with optimized transistor dimensions. Simulated output waveforms of the full-adder circuit with optimized transistor dimensions, showing the signal propagation delay during the same worst-case transition. MU 1 8 23 2Z4 25b The full-adder circuit designed in this example can now be used as the basic building block of an 8-bit binary adder, which accepts two 8-bit binary numbers as input and produces the binary sum at the output.

    The simplest such adder can be constructed by a cascade-connection of eight full adders, where each adder stage performs a two-bit addition, produces the corresponding sum bit, and passes the carry output on to the next stage. Hence, this cascade-connected adder configuration is called the carry ripple adder Fig. The overall speed of the carry ripple adder is obviously limited by the delay of the carry bits rippling through the carry chain; therefore, a fast carryout response becomes essential for the overall performance of the adder chain.

    Block diagram of a carry ripple adder chain consisting of full adders. Note that the input signals Ai and Bi are applied to a row of pins along the lower boundary of the array, while the output signals Si sum bits are made available along the upper boundary of the array. This arrangement of the input and output pins simplifies signal routing by placing the inputbus below, and the outputbus above the adder array.

    Mask layout of the 8-bit carry ripple adder array. C, Such structures are routinely used in circuits where a large number of arithmetic operations are required, such as arithmetic-logic units ALUs and digital signal processing DSP circuits. The overall performance of the multi-bit adder can be further increased by various measures, and some of these issues will be discussed in later chapters.

    The simulated input and output waveforms ofthe 8-bitbinary adder circuit are shown in Fig. It can be seen that the sumbit ofthe last adder stage is typically generated last, and the overall delay can be as much as 7 ns. Simulated input and output waveforms of the 8-bit carry ripple adder circuit, showing a maximum signal propagation delay of about 7 ns. This example has shown us that the design of CMOS digital integrated circuits involves a wide range of issues, from Boolean logic to gate-level design, to transistor- level design, to physical layout design, and to parasitics extraction followed by detailed circuit simulation for design tuning and performance verification.

    In essence, the final output of integrated circuit design is the mask data from which the actual circuit is fabricated. Thus, it is important to design the layout and, hence, the mask set such that the fabricated integrated circuits meet test specifications with a high yield.

    To achieve such a goal, designers perform extensive simulations using computer models extracted from the layout data and iterate the design until simulated results meet the specifications with sufficient margins. In the following chapters, we will discuss the fabrication of MOS transistors using a set of masks, layout design rules, and electrical 'properties of MOS transistors and their computer models, before discussing the most basic CMOS inverter circuit.

    Introduction In this chapter, the fundamentals ofMOS chip fabrication will be discussed and the major steps of the process flow will be examined.

    It is not the aim of this chapter to present a detailed discussion of silicon fabrication technology, which deserves separate treatment in a dedicated course. Rather, the emphasis will be on the general outline of the process flow and on the interaction of various processing steps, which ultimately determine the device and the circuit performance characteristics. The following chapters show that there are very strong links between the fabrication process, the circuit design process, and the performance of the resulting chip.

    Hence, circuit designers must have a working knowledge ofchip fabrication to create effective designs and to optimize the circuits with respect to various manufacturing parameters. Also, the circuitdesigner must have a clear understanding ofthe roles of various masks used in the fabrication process, and how the masks are used to define various features of the devices on-chip.

    The following discussion will concentrate on the well-established CMOS fabrica- tion technology, which requires that both n-channel nMOS and p-channel pMOS transistors be built on the same chip substrate. To accommodate both nMOS and pMOS devices, special regions must be created in which the semiconductor type is opposite to the substrate type. These regions are called wells or tubs. A p-well is created in an n-type substrate or, alternatively, an n-well is created in a p-type substrate.

    In the simple n-well CMOS fabrication technology presented here, the nMOS transistor is created in the p- type substrate, and the pMOS transistor is created in the n-well, which is built into the p- type substrate. In the twin-tub CMOS technology, additional tubs ofthe same type as the substrate can also be created for device optimization.

    The simplified process sequence for the fabrication ofCMOS integrated circuits on a p-type silicon substrate is shown in Fig. The process starts with the creation of the n-well regions for pMOS transistors, by impurity implantation into the substrate.

    The thin gate oxide is subsequently grown on the surface through thermal oxidation. Simplified process sequence for the fabrication of the n-well CMOS integrated circuit with a single polysilicon layer, showing only major fabrication steps. The process flow sequence pictured in Fig.

    To obtain a better understanding of the issues involved in the semiconductor fabrication process, we first have to consider some of the basic steps in more detail. Fabrication Process Flow: Basic Steps Note that each processing step requires that certain areas are defined on chip by appropriate masks. Consequently, the integrated circuit may be viewed as a set of In general, a layer must be patterned before the next layer ofmaterial is applied on the chip. The process used to transfer a pattern to a layer on the chip is called lithography.

    Since each layer has its own distinct patterning requirements, the lithographic sequence must be repeated for every layer, using a different mask. To illustrate the fabrication steps involved in patterning silicon dioxide through optical lithography, letus first examine the process flow shown in Fig.

    The sequence Si - substrate Exposedphotoresist becomessoluble Si - substrate a b c d Figure2. Process steps required for patterning of silicon dioxide. Si -substrate Si -substrate e f 9 Figure2. Process steps required for patterning of silicon dioxide continued.

    The entire oxide surface is then covered with a layer ofphotoresist,which is essentially a light-sensitive, acid-resistant organic polymer, initially insoluble in the developing solution Fig. If the photoresist material is exposed to ultraviolet UV light, the exposed areas become soluble so that they are no longer resistant to etching solvents.

    To selectively expose the photoresist, we have to cover some of the areas on the surface with a mask during exposure. Thus, when the structure with the mask on top is exposed to UV light, areas which are covered by the opaque features on the mask are shielded. In the areas where the UV light can pass through, on the other hand, the photoresist is exposed and becomes soluble Fig.

    The process sequence shown in Fig. There is another type of photoresist which is initially soluble and becomes insoluble hardened after exposure to UV light, called negative photoresist. If negative photoresist is used in the photolithography process, the areas which are not shielded from the UV light by the opaque mask features become insoluble, whereas the shielded areas can subsequently be etched away by a developing solution.

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    Negative photoresists are more sensitive to light, but their photolithographic resolution is not as high asthat ofthe positive photoresists. Therefore, negative photoresists are-used less commonly in the manufacturing of high-density integrated circuits. Following the UV exposure step, the unexposed portions of the photoresist can be removed by a solvent. Now, the silicon dioxide regions which are not covered by hardened photoresist can be etched away either by using a chemical solvent HF acid or by using a dry etch plasma etch process Fig.

    Note that at the end ofthis step, we obtain an oxide window that reaches down to the silicon surface Fig. The remaining photoresist can now be stripped from the silicon dioxide surface by using another solvent, leaving the patterned silicon dioxide feature on the surface as shown in Fig. The sequence of process steps illustrated in detail in Fig.

    The fabrication of semiconductor devices requires several such pattern transfers to be performed on silicon dioxide, polysilicon, and metal. The basic patterning process used in all fabrication steps, however, is quite similar to the one shown in Fig.

    Also note Si -substrate Figure2. The result of a single lithographic patterning sequence on silicon dioxide, without showing the intermediate steps. Compare the unpatterned structure top and the patterned structure bottom with Fig. In the following, the main processing steps involved in the fabrication of an n-channel MOS transistor on a p-type silicon substrate will be examined.

    Then, the field oxide is selectively etched to expose the silicon surface on which the MOS transistor will be created Fig. Following this step, the surface is covered with a thin, high-quality oxide layer, which will eventually form the gate oxide of theMOS transistor Fig.

    Si -substrate Si -substrate Si -substrate b c d Si -substrate L: Addi t ion Then, the fielc the MOS transistor covered with a thin, hi of the MOS transistor ration of high-density patterns required in sub-micron devices, tm lithography is used instead of optical lithography. In the -ocessing steps involved in the fabrication of an n-channel MOS 3ilicon substrate will be examined. Following this step, the surface is gh-quality oxide layer, which will eventually form the gate oxide Fig.

    On top of the thin oxide layer, a layer of polysilicon Undoped polysilicon has relatively high resistivity. The-resistivity of polysilicon can be reduced, however, by doping it with impurity atoms. After deposition, the polysilicon layer is patterned and etched to form the intercon- nects and the MOS transistor gates Fig. The thin gate oxide not covered by polysilicon is also etched away, which exposes the bare silicon surface on which the source and drainjunctions are to be formed Fig.

    The entire silicon surface is then doped with a high concentration of impurities, either through diffusion or ion implanta- tion in this case with donor atoms to produce n-type doping. Figure 2. The impurity doping also penetrates the polysilicon on the surface, reducing its resistivity. Note that the Polysilicon Thin oxide. Process flow for the fabrication of an n-type MOS transistor continued. DA-vcl1r- rue Since this procedure allows very precise positioning of the two regions relative to the gate, it is also called the self-alignedprocess.

    Once the source and drain regions are completed, the entire surface is again covered with an insulating layer of silicon dioxide Fig. The insulating oxide layer is then patterned in order to provide contact windows for the drain and source junctions Fig. The surface is covered with evaporated aluminum which will form the intercon- nects Fig. Finally, the metal layer is patterned and etched, completing the interconnection ofthe MOS transistors on the surface Fig.

    The major process steps for the fabrication of an nMOS transistor on p-type silicon substrate are also illustrated in Plate 1and Plate 2. Device Isolation Techniques The MOS transistors that comprise an integrated circuit must be electrically isolated from each other during fabrication. Isolation is required to prevent unwanted conduction paths between the devices, to avoid creation of inversion layers outside the channel regions of transistors, and to reduce leakage currents.

    To achieve a sufficient level of electrical isolation between neighboring transistors on a chip surface, the devices are typically created in dedicated regions called active areas, where each active area is surrounded by a relatively thick oxide barrier called the field oxide.

    One possible technique to create isolated active areas on silicon surface is first to grow a thick field oxide over the entire surface of the chip, and then to selectively etch the oxide in certain regions, to define the active areas.

    This fabrication technique, called etchedfield-oxideisolation,is already illustrated in Fig. Although the technique is relatively straightforward, it also has 29 some drawbacks. The most significant disadvantage is that the thickness of the field oxide leads to rather large oxide steps atthe boundaries between active areas and isolation Fabrication field regions.

    When polysilicon and metal layers are deposited over such boundaries in of MOSFETs subsequent process steps, the sheer height difference at the boundary can cause cracking of deposited layers, leading to chip failure. To prevent this, most manufacturers prefer isolation techniques that partially recess the field oxide into the silicon surface, resulting in a more planar surface topology. Selective oxide growth is achieved by shielding the active areas with silicon nitride Si3 N4 during oxidation, which effectively inhibits oxide growth.

    First, a thin pad oxide also called stress-relief oxide is grown onthe silicon surface, followed by the deposition and patterning of a silicon nitride layer tomask i.

    The thin pad oxide underneath the silicon nitride layer is used to protect the silicon surface from stress caused by nitride during the subsequent process steps. The exposed areas of the silicon surface, which will eventually form the isolation regions, are doped with a p-type impurity to create the channel-stop implants that surround the transistors Fig.

    Next, a thick field oxide is grown in the areas not covered with silicon nitride, as shown in Fig. Notice that the field oxide is partially recessed into the surface since the thermal oxidation process also consumes some of the silicon. Also, the field oxide forms a lateral extension under the nitride layer, called the bird's beak region.

    This lateral encroachment is mainly responsible for a reduction of the active area. The silicon nitride layer and the thin pad oxide layer are etched in the final step Fig. The LOCOS process is a popular technique used for achieving field oxide isolation with a more planar surface topology.

    The CMOS n-Well Process Having examined the basic process steps for pattern transfer through lithography and having gone through the fabrication procedure ofa single n-type MOS transistor, we can now return to the generalized fabrication sequence of n-well CMOS integrated circuits, as shown in Fig. In the following figures, some of the important process steps involved in the fabrication of a CMOS inverter will be shown by a top view of the lithographic masks and a cross-sectional view of the relevant areas.

    The n-well CMOS process starts with a moderately doped with impurity concentra- tion typically less than cm-3 p-type silicon substrate. Then, an initial oxide layer is grown on the entire surface.

    The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. Figures 2. Si -substrate Field oxide lo EI- , Following thecreation ofthe n-well region, athick field oxide is grown in the areas surrounding the transistor's active regions, and a thin gate oxide is grown on top of the active regions.

    The thickness and the quality of the gate oxide are two of the most critical fabrication parameters, since they strongly affect theoperational characteristics oftheMOS transistor, as well as its long-term reliability.

    Maly [1]. C Figure2. The polysilicon layer is deposited using chemical vapor deposition CVD and patterned by dry plasma etching.

    Hot-Carrier Reliability of MOS VLSI Circuits

    The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step. Also, the ohmic contacts to the substrate and to the n-well are implanted in this process step. Also, the ohmic contacts to the substrate and to the n-well are [anted in this process step.

    Maly [ An insulating silicon dioxide layer is deposited over the entire wafer using CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon contact windows.

    These contact windows are necessary to complete the circuit interconnections using the metal layer, which is patterned in the next step. Metal aluminum is deposited over the entire chip surface using metal evapora- tion, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are ultimately essential for circuit reliability.

    The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor in the n-well , and the polysilicon and metal interconnec- tions. The final step is to deposit the passivation layer for protection over the chip, except over wire-bonding pad areas. Layout Design Rules The physical mask layout of any circuit to be manufactured using a particular process must conform to a set ofgeometric constraints or rules, which are generally called layout design rules.

    These rules usually specify the minimum allowable line widths forphysical objects on-chip such as metal and polysilicon interconnects or diffusion areas, minimum feature dimensions, and minimum allowable separations between two such features. If ametal line width is made too small, for example, it is possible for the line to break during the fabrication process or afterwards, resulting in an open circuit. If two lines are placed too close to each other in the layout, they may form an unwanted short circuit by merging during or after the fabrication process.

    The main objective of design rules is to achieve, for any circuit to be manufactured with a particular process, a high overall yield and reliability while using the smallest possible silicon area. Note that there is usually a trade-off between higher yield, which is obtained through conservative geometries, and better area efficiency, which is obtained through aggres- sive, high-density placement of various features on the chip. The layout design rules which are specified for a particular fabrication process normally represent a reasonable optimum point in terms of yield and density.

    It must be emphasized, however, that the design rules do not represent strict boundaries which separate "correct" designs from "incorrect" ones. To summarize, we can say, in general, that observing the layout design rules significantly increases the probability offabricating a successful product with highyield.

    The design rules are usually described in two ways: Lambda-based layout design rules were originally devised to simplify the industry- standard micron-based design rules and to allow scaling capability for various processes. It must be emphasized, however, that most ofthe submicron CMOS process design rules do not lend themselves to straightforward linear scaling.

    The use of lambda-based design rules must therefore be handled with caution in submicron geometries. R41 "ro l ml. Lj The design of physical layout is very tightly linked to overall circuit performance area, speed, and power dissipation since the physical structure directly determines the transconductances of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area which is used for a certain function.

    Therefore, automated layout generation e. In order to judge the physical constraints and limitations, however, the VLSI designer must also have a good understanding of the physical mask layout process. The physical mask layout design of CMOS logic gates is an iterative process which starts with the circuit topology to realize the desired logic function and the initial sizing of the transistors to realize the desired performance specifications.

    At this point, the designer can only estimate the total parasitic load at the output node, based on the fan- out, the number of devices, and the expected length of the interconnection lines. If the logic gate contains more than 4 to 6 transistors, the topological graph representation and the Euler-path method allow the designer to determine the optimum ordering of the transistors see Chapter 7.

    Asimple stick diagram layout can now be drawn, showing the locations of the transistors, the local interconnections between the transistors, and the locations of the contacts. After a topologically feasible layout is found, the mask layers are drawn using a layout editor tool according to the layout design rules. This procedure may require several small iterations in order to accommodate all the design rules, but the basic topology should not change very significantly.

    Following the final DRC Design Rule Check , a circuit extraction procedure is performed on the-finished layout to determine the actual transistor sizes, and more importantly, the parasitic capacitances at each node.

    The result of the extraction step is usually a detailed SPICE input file, which is automatically generated bythe extraction tool. Now, the actual performance ofthe circuit can be determined by performing a SPICE simulation, using the extracted net-list. If the simulated circuit performance e. The designer may also decide to change parts or all ofthe circuit topology in order to reduce the parasitics.

    The flow diagram of this iterative process is shown in Fig. First, we need to create the individual transistors according to the design rules.

    Assume that we attempt to design the inverter with minimum-size transistors. The width of the active area is then determined 40 Typical design flow for the production of a mask layout.

    The width of the polysilicon line over the active area which is the gate of the transistor is typically taken as the minimum poly width Fig. Then, the minimum overall length of the active area is determined by the following sum: Design rules which determine the dimensions of aminimum-size transistor. The polysilicon gates of the nMOS and the pMOS transistors are usually aligned, so that the gate connections can be made with a singlepolysilicon line ofleastpossible length.

    The reason foravoiding long polysilicon connections as a general layout practice is the fact that the large parasitic resistance and the parasitic capacitance of polysilicon lines may result in significant RC delays; Thus, even local signal connections are preferably made with metal lines as much as possible, and metal-polysilicon contacts are used to provide the electrical connection between the two layers, wherever necessary.

    Thedimensions ofmetal lines in a mask layout are usually dictated by the minimum metal width and the minimum metal separation between two neighboring lines, on the same level. Notice that in order to be biased properly, the n-well region must also have a VDD contact.

    Having examined the main steps of a typical CMOS inverter mask layout design, we have to emphasize that this example obviously represents only one of many possibilities for the layout of this circuit. The layout design rules dictate a set of limitations for the mask geometry, yet the full-custom layout design process still allows a large number of variations in terms ofdevice sizing, the placement of individual devices, and the routing of interconnections between the devices; even for a simple circuit consisting ofonly two transistors.

    Notice that the number of layout possibilities also tends to increase with circuit complexity, i. Complete mask layout of the CMOS inverter. References 1. Van Nostrand Rheinhold, Prentice-Hall, Inc.

    McGraw-Hill, Chang and S. Wolf and R. Fabrication Volume 1 , Lattice Press, Process Integration Volume 2 , Lattice Press, Exercise Problems 2. The minimum feature size allowed is 1gim for line width and window opening. Also, 0. What would be the effect ofwindow design onthe resistance?

    Discuss at least two other mechanisms in the processing thatcan make the processed resistance deviate from the target value even if the effect of the window is neglected. Discuss the pros and cons ofhaving the line width at a minimum as compared to making the width larger than the minimum width. This process can reduce the nominal sheet resistance from 20 Q to 2 Q or even less.

    For the same purpose, silicide material is also deposited on top of source and drain diffusions in MOS transistors. Thus, a single-step deposition ofsilicide can be achieved onpolysilicon gates and source and drain regions of MOS transistors.